Integrated circuit memory devices typically include one or more arrays of memory cells that store data. The data is either read from or written to the memory cell using data communication connections. Some example memory devices include but are not limited to random access memories (RAM), dynamic random access memories (DRAM), Synchronous DRAM (SDRAM), static RAM (SRAM), and non-volatile memories such as FLASH.
During production of the memory devices, the individual memory cells need to be tested. Thus, data is written to the memory cells and then the data is read from the memory. As the density of the memory arrays increase, the time and cost needed to fully test the memory array also increases. For example, a common testing procedure for a memory connected to a memory tester is to first have the tester send a command to the memory to erase all of its bits to “1”. The tester then reads the memory cells to verify that they are all “1”. Next, zeros are written to all of the bits of the memory and the cells are read in order to verify that they are all “0”. Then, all of the bits of the memory are erased, a checkerboard pattern is written to the memory and the cells are read in order to verify that the checkerboard pattern is present. Finally, all of the bits of the memory are erased, an inverted checkerboard pattern is written to the memory, and the cells are read in order to verify that the inverted checkerboard pattern is present. This testing procedure is a good way to find out if any of the bits of the memory are shorted to an adjacent bit, to a high level, or to a low state, or if there are any other problems.
Because the cost of testing has becoming a significant component of the total manufacturing cost of memory chips, testing using compressed data lines can be implemented. See U.S. Pat. No. 5,787,097 entitled “Output Data Compression Scheme for Use in Testing IC Memories,” issued Jul. 28, 1998. This patent describes a system for compressing data during a test operation so that multiple memory devices can be simultaneously tested using a common tester. Thus, less data communication connections (DQ's) are required for a given number of memory cells when implementing data compression.
One deficiency of read compression is the identification of a defective location. That is, if an error is detected during testing a full non-compressed read operation may be needed to identify the defect location for redundant repair. A non-compressed test operation requires all of the DQ's, and is counter productive to the compressed testing scheme.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device with improved test operations.